Integrated circuits are typically fabricated onto and within semiconductor substrates, with the continuing trend being towards ever-smaller devices. Different areas of the substrate over which an integrated circuit is fabricated might be at different heights or elevations relative to the substrate. For example, and by way of example only, one area of circuitry might be fabricated deeper within bulk semiconductive material than are circuit components in an adjacent area of the substrate. The difference in elevations where the individual components are fabricated can differ by thousands of Angstroms.
Further, it is often desirable to electrically connect a component in one of these circuitry areas with a component in another circuitry area at the different elevation. Such is typically accomplished by deposition of one or more conductive materials and the subtractive patterning and etching thereof to form what is commonly referred to as a “local interconnect”. It can, however, be difficult to pattern electrically conductive lines which vary over outer elevation by thousands of Angstroms, particularly over adjacent areas of a substrate.
While the invention was motivated in addressing the above identified issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.